Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

• Main Authors: Kok, C.K., Chew, W.C., Chim, W.K., Chan, D.S.H., Leang, S.E.
• Other Authors: ELECTRICAL ENGINEERING
• Format: Conference or Workshop Item
• Published: 2014
• Online Access: http://scholarbank.nus.edu.sg/handle/10635/72523
• Institution: National University of Singapore

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA