DC voltage-voltage method to measure the interface traps in sub-micron MOSTs

10.1088/0268-1242/14/7/306

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Main Authors:	Jie, B.B., Li, M.F., Chim, W.K., Chan, D.S.H., Lo, K.F.
Other Authors:	ELECTRICAL ENGINEERING
Format:	Article
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/80344
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Institution:	National University of Singapore

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spelling	sg-nus-scholar.10635-803442023-10-25T21:59:33Z DC voltage-voltage method to measure the interface traps in sub-micron MOSTs Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F. ELECTRICAL ENGINEERING 10.1088/0268-1242/14/7/306 Semiconductor Science and Technology 14 7 621-627 SSTEE 2014-10-07T02:56:29Z 2014-10-07T02:56:29Z 1999-07 Article Jie, B.B., Li, M.F., Chim, W.K., Chan, D.S.H., Lo, K.F. (1999-07). DC voltage-voltage method to measure the interface traps in sub-micron MOSTs. Semiconductor Science and Technology 14 (7) : 621-627. ScholarBank@NUS Repository. https://doi.org/10.1088/0268-1242/14/7/306 02681242 http://scholarbank.nus.edu.sg/handle/10635/80344 000081450400007 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
description	10.1088/0268-1242/14/7/306
author2	ELECTRICAL ENGINEERING
author_facet	ELECTRICAL ENGINEERING Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F.
format	Article
author	Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F.
spellingShingle	Jie, B.B. Li, M.F. Chim, W.K. Chan, D.S.H. Lo, K.F. DC voltage-voltage method to measure the interface traps in sub-micron MOSTs
author_sort	Jie, B.B.
title	DC voltage-voltage method to measure the interface traps in sub-micron MOSTs
title_short	DC voltage-voltage method to measure the interface traps in sub-micron MOSTs
title_full	DC voltage-voltage method to measure the interface traps in sub-micron MOSTs
title_fullStr	DC voltage-voltage method to measure the interface traps in sub-micron MOSTs
title_full_unstemmed	DC voltage-voltage method to measure the interface traps in sub-micron MOSTs
title_sort	dc voltage-voltage method to measure the interface traps in sub-micron mosts
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/80344
_version_	1781783900191719424

DC voltage-voltage method to measure the interface traps in sub-micron MOSTs

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