DC voltage-voltage method to measure the interface traps in sub-micron MOSTs
10.1088/0268-1242/14/7/306
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Main Authors: | Jie, B.B., Li, M.F., Chim, W.K., Chan, D.S.H., Lo, K.F. |
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Other Authors: | ELECTRICAL ENGINEERING |
Format: | Article |
Published: |
2014
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Online Access: | http://scholarbank.nus.edu.sg/handle/10635/80344 |
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Institution: | National University of Singapore |
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