Via design optimization for high speed device packaging
Proceedings of the Electronic Packaging Technology Conference, EPTC
Saved in:
Main Authors: | Low, Hong-Guan, Iyer, Mahadevan K., Ooi, Ban-Leong, Leong, Mook-Seng |
---|---|
Other Authors: | INSTITUTE OF MICROELECTRONICS |
Format: | Article |
Published: |
2014
|
Online Access: | http://scholarbank.nus.edu.sg/handle/10635/81348 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | National University of Singapore |
Similar Items
-
Via design optimization for high speed device packaging
by: Low, Hong-Guan, et al.
Published: (2014) -
Novel method for Simultaneous Switching Noise analysis in electronic packages
by: Jin, Zhang, et al.
Published: (2014) -
Novel method for Simultaneous Switching Noise analysis in electronic packages
by: Jin, Zhang, et al.
Published: (2014) -
Design and characterization of interposers for high speed fine pitch wafer level packaged device testing
by: TAN PANG HOAW, JIMMY
Published: (2011) -
Design and optimization of packaged integrated antenna
by: Chua, C.-P., et al.
Published: (2014)