Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices
International Journal of Electronics
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2014
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sg-nus-scholar.10635-818152015-01-27T18:07:57Z Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices Samudra, G. Rajendran, K. ELECTRICAL ENGINEERING International Journal of Electronics 87 5 513-530 IJELA 2014-10-07T03:12:20Z 2014-10-07T03:12:20Z 2000-05 Review Samudra, G.,Rajendran, K. (2000-05). Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices. International Journal of Electronics 87 (5) : 513-530. ScholarBank@NUS Repository. 00207217 http://scholarbank.nus.edu.sg/handle/10635/81815 NOT_IN_WOS Scopus |
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International Journal of Electronics |
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ELECTRICAL ENGINEERING |
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ELECTRICAL ENGINEERING Samudra, G. Rajendran, K. |
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Samudra, G. Rajendran, K. |
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Samudra, G. Rajendran, K. Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices |
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Samudra, G. |
title |
Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices |
title_short |
Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices |
title_full |
Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices |
title_fullStr |
Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices |
title_full_unstemmed |
Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices |
title_sort |
comparative analysis of minimum surface potential and location of barrier peaks in various si mosfet devices |
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2014 |
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http://scholarbank.nus.edu.sg/handle/10635/81815 |
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