A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance

10.1109/LED.2007.914100

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Bibliographic Details
Main Authors:	Toh, E.-H., Wang, G.H., Chan, L., Samudra, G., Yeo, Y.-C.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Subjects:	Device optimization Impact ionization Impact-ionization MOS (I-MOS) Subthreshold swing
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/81860
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-81860
record_format	dspace
spelling	sg-nus-scholar.10635-818602023-10-26T20:38:06Z A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance Toh, E.-H. Wang, G.H. Chan, L. Samudra, G. Yeo, Y.-C. ELECTRICAL & COMPUTER ENGINEERING Device optimization Impact ionization Impact-ionization MOS (I-MOS) Subthreshold swing 10.1109/LED.2007.914100 IEEE Electron Device Letters 29 2 189-191 EDLED 2014-10-07T04:22:33Z 2014-10-07T04:22:33Z 2008-02 Article Toh, E.-H., Wang, G.H., Chan, L., Samudra, G., Yeo, Y.-C. (2008-02). A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance. IEEE Electron Device Letters 29 (2) : 189-191. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2007.914100 07413106 http://scholarbank.nus.edu.sg/handle/10635/81860 000252622800018 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	Device optimization Impact ionization Impact-ionization MOS (I-MOS) Subthreshold swing
spellingShingle	Device optimization Impact ionization Impact-ionization MOS (I-MOS) Subthreshold swing Toh, E.-H. Wang, G.H. Chan, L. Samudra, G. Yeo, Y.-C. A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
description	10.1109/LED.2007.914100
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Toh, E.-H. Wang, G.H. Chan, L. Samudra, G. Yeo, Y.-C.
format	Article
author	Toh, E.-H. Wang, G.H. Chan, L. Samudra, G. Yeo, Y.-C.
author_sort	Toh, E.-H.
title	A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
title_short	A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
title_full	A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
title_fullStr	A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
title_full_unstemmed	A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
title_sort	double-spacer i-mos transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/81860
_version_	1781784000932610048

A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance

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