Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature

Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature

10.1109/LED.2011.2106757

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Bibliographic Details
Main Authors: Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Article
Published: 2014
Subjects:
CMOS technology
gate-all-around (GAA)
subthreshold swing (SS)
top-down
tunneling field-effect transistor (TFET)
vertical silicon nanowire (NW) (SiNW)
Online Access:http://scholarbank.nus.edu.sg/handle/10635/83258
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Institution: National University of Singapore

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http://scholarbank.nus.edu.sg/handle/10635/83258

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