Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature

10.1109/LED.2011.2106757

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Bibliographic Details
Main Authors:	Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Article
Published:	2014
Subjects:	CMOS technology gate-all-around (GAA) subthreshold swing (SS) top-down tunneling field-effect transistor (TFET) vertical silicon nanowire (NW) (SiNW)
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/83258
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-83258
record_format	dspace
spelling	sg-nus-scholar.10635-832582024-11-10T21:13:25Z Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature Gandhi, R. Chen, Z. Singh, N. Banerjee, K. Lee, S. ELECTRICAL & COMPUTER ENGINEERING CMOS technology gate-all-around (GAA) subthreshold swing (SS) top-down tunneling field-effect transistor (TFET) vertical silicon nanowire (NW) (SiNW) 10.1109/LED.2011.2106757 IEEE Electron Device Letters 32 4 437-439 EDLED 2014-10-07T04:39:09Z 2014-10-07T04:39:09Z 2011-04 Article Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S. (2011-04). Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature. IEEE Electron Device Letters 32 (4) : 437-439. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2011.2106757 07413106 http://scholarbank.nus.edu.sg/handle/10635/83258 000288664800003 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
topic	CMOS technology gate-all-around (GAA) subthreshold swing (SS) top-down tunneling field-effect transistor (TFET) vertical silicon nanowire (NW) (SiNW)
spellingShingle	CMOS technology gate-all-around (GAA) subthreshold swing (SS) top-down tunneling field-effect transistor (TFET) vertical silicon nanowire (NW) (SiNW) Gandhi, R. Chen, Z. Singh, N. Banerjee, K. Lee, S. Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature
description	10.1109/LED.2011.2106757
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Gandhi, R. Chen, Z. Singh, N. Banerjee, K. Lee, S.
format	Article
author	Gandhi, R. Chen, Z. Singh, N. Banerjee, K. Lee, S.
author_sort	Gandhi, R.
title	Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature
title_short	Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature
title_full	Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature
title_fullStr	Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature
title_full_unstemmed	Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature
title_sort	vertical si-nanowire n-type tunneling fets with low subthreshold swing ≤50 mv/decade) at room temperature
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/83258
_version_	1821200430304067584

Vertical Si-Nanowire n-type tunneling FETs with low subthreshold swing ≤50 mV/decade) at room temperature

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