Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation

Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation

10.1109/FPL.2013.6645498

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Bibliographic Details
Main Authors: Das, A., Venkataraman, S., Kumar, A.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/83835
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Institution: National University of Singapore
Description
Summary:10.1109/FPL.2013.6645498

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