Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation

10.1109/FPL.2013.6645498

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Bibliographic Details
Main Authors:	Das, A., Venkataraman, S., Kumar, A.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/83835
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Institution:	National University of Singapore

id	sg-nus-scholar.10635-83835
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spelling	sg-nus-scholar.10635-838352015-02-03T13:10:51Z Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation Das, A. Venkataraman, S. Kumar, A. ELECTRICAL & COMPUTER ENGINEERING 10.1109/FPL.2013.6645498 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings - 2014-10-07T04:45:45Z 2014-10-07T04:45:45Z 2013 Conference Paper Das, A.,Venkataraman, S.,Kumar, A. (2013). Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation. 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings : -. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/FPL.2013.6645498" target="_blank">https://doi.org/10.1109/FPL.2013.6645498</a> http://scholarbank.nus.edu.sg/handle/10635/83835 NOT_IN_WOS Scopus
institution	National University of Singapore
building	NUS Library
country	Singapore
collection	ScholarBank@NUS
description	10.1109/FPL.2013.6645498
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Das, A. Venkataraman, S. Kumar, A.
format	Conference or Workshop Item
author	Das, A. Venkataraman, S. Kumar, A.
spellingShingle	Das, A. Venkataraman, S. Kumar, A. Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation
author_sort	Das, A.
title	Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation
title_short	Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation
title_full	Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation
title_fullStr	Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation
title_full_unstemmed	Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation
title_sort	improving autonomous soft-error tolerance of fpga through lut configuration bit manipulation
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/83835
_version_	1681089508931534848

Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation

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