Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory

Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory

10.1109/IEDM.2007.4418868

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Bibliographic Details
Main Authors: Fu, J., Buddharaju, K.D., Teo, S.H.G., Zhu, C., Yu, M.B., Singh, N., Lo, G.Q., Balasubramanian, N., Kwong, D.L.
Other Authors: ELECTRICAL & COMPUTER ENGINEERING
Format: Conference or Workshop Item
Published: 2014
Online Access:http://scholarbank.nus.edu.sg/handle/10635/84323
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Institution: National University of Singapore
Description
Summary:10.1109/IEDM.2007.4418868

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