Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory

• Main Authors: Fu, J., Buddharaju, K.D., Teo, S.H.G., Zhu, C., Yu, M.B., Singh, N., Lo, G.Q., Balasubramanian, N., Kwong, D.L.
• 其他作者: ELECTRICAL & COMPUTER ENGINEERING
• 格式: Conference or Workshop Item
• 出版: 2014
• 在線閱讀: http://scholarbank.nus.edu.sg/handle/10635/84323
• 機構: National University of Singapore

10.1109/IEDM.2007.4418868