Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory

10.1109/IEDM.2007.4418868

Saved in:

Bibliographic Details
Main Authors:	Fu, J., Buddharaju, K.D., Teo, S.H.G., Zhu, C., Yu, M.B., Singh, N., Lo, G.Q., Balasubramanian, N., Kwong, D.L.
Other Authors:	ELECTRICAL & COMPUTER ENGINEERING
Format:	Conference or Workshop Item
Published:	2014
Online Access:	http://scholarbank.nus.edu.sg/handle/10635/84323
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	National University of Singapore

id	sg-nus-scholar.10635-84323
record_format	dspace
spelling	sg-nus-scholar.10635-843232023-10-25T22:15:41Z Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L. ELECTRICAL & COMPUTER ENGINEERING 10.1109/IEDM.2007.4418868 Technical Digest - International Electron Devices Meeting, IEDM 79-82 TDIMD 2014-10-07T04:51:22Z 2014-10-07T04:51:22Z 2007 Conference Paper Fu, J., Buddharaju, K.D., Teo, S.H.G., Zhu, C., Yu, M.B., Singh, N., Lo, G.Q., Balasubramanian, N., Kwong, D.L. (2007). Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory. Technical Digest - International Electron Devices Meeting, IEDM : 79-82. ScholarBank@NUS Repository. https://doi.org/10.1109/IEDM.2007.4418868 01631918 http://scholarbank.nus.edu.sg/handle/10635/84323 000259347800016 Scopus
institution	National University of Singapore
building	NUS Library
continent	Asia
country	Singapore Singapore
content_provider	NUS Library
collection	ScholarBank@NUS
description	10.1109/IEDM.2007.4418868
author2	ELECTRICAL & COMPUTER ENGINEERING
author_facet	ELECTRICAL & COMPUTER ENGINEERING Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L.
format	Conference or Workshop Item
author	Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L.
spellingShingle	Fu, J. Buddharaju, K.D. Teo, S.H.G. Zhu, C. Yu, M.B. Singh, N. Lo, G.Q. Balasubramanian, N. Kwong, D.L. Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
author_sort	Fu, J.
title	Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
title_short	Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
title_full	Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
title_fullStr	Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
title_full_unstemmed	Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory
title_sort	trap layer engineered gate-all-around vertically stacked twin si -nanowire nonvolatile memory
publishDate	2014
url	http://scholarbank.nus.edu.sg/handle/10635/84323
_version_	1781784441634422784

Trap layer engineered gate-all-around vertically stacked twin Si -nanowire nonvolatile memory

Similar Items