FPGA BASED HARDWARE ACCELERATOR DESIGN FOR DEEP CONVOLUTIONAL NEURAL NETWORK

FPGA BASED HARDWARE ACCELERATOR DESIGN FOR DEEP CONVOLUTIONAL NEURAL NETWORK

The development of hardware accelerators for deep learning is increasing rapidly with the purpose for flexibility to be applied to various deep learning architectures. Accelerators that are widely marketed today are accelerators with GPU-based architectures where developers encounter quite a l...

Full description

Saved in:

Bibliographic Details
Main Author:	Dwi Cahyo, Ardian
Format:	Theses
Language:	Indonesia
Online Access:	https://digilib.itb.ac.id/gdl/view/58018
Tags:	Add Tag No Tags, Be the first to tag this record!
Institution:	Institut Teknologi Bandung
Language:	Indonesia

Similar Items

Accelerator of convolution neural networks based on FPGA
by: Yu, Guohao
Published: (2017)

Quantum correction hardware accelerator design on FPGA
by: Cao, Hongyu
Published: (2023)

Quantum correction hardware accelerator design on FPGA
by: Soh, Siang Yang
Published: (2024)

FPGA library based design of a hardware model for convolutional neural network with automated weight compression using K-means clustering
by: Yap, Roderick, et al.
Published: (2019)

Implementation of a convolutional neural network on FPGA
by: Xue, Can
Published: (2018)

Comparison between GPU and FPGA as hardware accelerator
by: Yang, Lu
Published: (2014)

A comparison between GPU and FPGA as hardware accelerators
by: Loh, Jason Keng Sang
Published: (2016)

Fast prototyping of neural network on hardware accelerator
by: Agus, Hans Kevin
Published: (2021)

FPGA BASED HARDWARE ACCELERATOR DESIGN OF A* ALGORITHM FOR GRID PATH PLANNING IN MOBILE ROBOT
by: Daffa Rasyid, Muhammad

Optimal placement-aware trace-based scheduling of hardware reconfigurations for FPGA accelerators
by: Sim, J.E., et al.
Published: (2013)

FPGA implementation of spiking convolutional neural networks for voice keyword recognition
by: Ng, Wei Soon
Published: (2021)

Python extension for a convolution neural network accelerator
by: Pattanapong Khaopaibul Wu Jing Han
Published: (2022)

DESIGN AND IMPLEMENTATION OF MULTI-ALGORITHM CRYPTOGRAPHY HARDWARE ACCELERATOR USING ARM PROCESSOR AND FPGA BASED ON CONTEXT SWITCH
by: Made Gita Narendra Kumara NIM - 23217071 , I

Hardware-friendly stochastic and adaptive learning in memristor convolutional neural networks
by: Zhang, Wei, et al.
Published: (2022)

Hardware acceleration of neural networks with CMOS and post-CMOS devices
by: Govind Narasimman
Published: (2017)

FPGA implementation of low-power real-time convolutional neural network inference
by: Gerlinghoff, Daniel
Published: (2020)

Image recognition based on deep learning of convolutional neural networks
by: Xie, Cong
Published: (2019)

AcceleNetor: FPGA-accelerated neural network implementation for side-channel analysis
by: Wang, Di
Published: (2023)

DESIGN OF LOW POWER, HARDWARE-AWARE ANALOG MEMORY-BASED ACCELERATORS FOR DEEP LEARNING
by: VELURI HASITA
Published: (2022)

HAPPINESS MEASUREMENT SERVICE DEVELOPMENT BASED ON DEEP CONVOLUTIONAL NEURAL NETWORK
by: Andrian, Rizky

Pavement defect detection with deep convolutional neural network
by: Chan, Zhen Yi
Published: (2023)

Towards efficient convolutional neural network for embedded hardware via multi-dimensional pruning
by: Kong, Hao, et al.
Published: (2023)

Implementation and performance evaluation of NVDLA based deep learning accelerator hardware
by: Song, Tin Chen
Published: (2021)

DESIGN SPACE EXPLORATION TECHNIQUES FOR FPGA-BASED ACCELERATORS
by: ZHONG GUANWEN
Published: (2017)

COMPARISON OF DEEP CONVOLUTIONAL GAUSSIAN PROCESS MODEL WITH CONVOLUTIONAL NEURAL NETWORK IN IMAGE CLASSIFICATION
by: Alexander Owen, Nelson

Vulnerability analysis on noise-injection based hardware attack on deep neural networks
by: Liu, Wenye, et al.
Published: (2020)

Deep convolutional neural network-based Bernoulli heatmap for head pose estimation
by: Hu, Zhongxu, et al.
Published: (2022)

Norm-based generalisation bounds for deep multi-class convolutional neural networks
by: LEDENT, Antoine, et al.
Published: (2021)

D-pruner: Filter-based pruning method for deep convolutional neural network
by: HUYNH, Nguyen Loc, et al.
Published: (2018)

D-pruner: Filter-based pruning method for deep convolutional neural network
by: HUYNH, Nguyen Loc, et al.
Published: (2018)

DESIGN AND IMPLEMENTATION OF BC3 ALGORITHM HARDWARE IN FPGA
by: (NIM: 23207024), HIDAYAT

Fault-injection based attacks and countermeasure on deep neural network accelerators
by: Liu, Wenye
Published: (2021)

Deep convolutional neural networks for manufactured IC image analysis
by: Tan, Weiwei
Published: (2019)

TOWARD A RUNTIME PROGRAMMABLE SPIKING NEURAL NETWORK HARDWARE ACCELERATOR WITH ON-CHIP LEARNING
by: NGUYEN NGOC NHU THAO
Published: (2023)

DeepSense: A GPU-based deep convolutional neural network framework on commodity mobile devices
by: HUYNH NGUYEN LOC,, et al.
Published: (2016)

Modelling, exploration and optimization of hardware accelerators for deep learning applications
by: Dutt, Arko
Published: (2023)

FPGA-based reconfigurable architecture for neural network
by: Sim, Ui Tek.
Published: (2008)

Subject adaptation with deep convolutional neural network for EEG-based motor imagery classification
by: Zhang, Kaishuo
Published: (2020)

DeepTronic: An electronic device classification model using deep convolutional neural networks
by: Salvador, Rodolfo C., et al.
Published: (2019)

DEEP AND SHALLOW VOLCANIC EVENT CLASSIFICATION USING CONVOLUTIONAL NEURAL NETWORK
by: SINAR GUNTARA - NIM : 12313020 , AMAJID