Hardware Implementation of an Iterative Parallel Scheduler for Optical Interconnection Networks
This paper proposes an iterative parallel scheduler for optical interconnection networks based on the longest queue first algorithm, presents an optimized hardware implementation in commercial FPGA boards, and experimentally assess its performance.
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Archīum Ateneo
2016
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在線閱讀: | https://archium.ateneo.edu/ecce-faculty-pubs/56 https://www.osapublishing.org/abstract.cfm?uri=Networks-2016-NeM3B.4 |
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