Low-power high-speed dual-modulus prescaler for Gb/s applications

Low-power high-speed dual-modulus prescaler for Gb/s applications

This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed a...

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Main Authors: Wang, Keping, Ma, Kaixue, Yeo, Kiat Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2013
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/101771
http://hdl.handle.net/10220/16362
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1017712020-03-07T13:24:50Z Low-power high-speed dual-modulus prescaler for Gb/s applications Wang, Keping Ma, Kaixue Yeo, Kiat Seng School of Electrical and Electronic Engineering IEEE Asia Pacific Conference on Circuits and Systems (2012 : Kaohsiung, Taiwan) DRNTU::Engineering::Electrical and electronic engineering This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed and low power consumption simultaneously. The prescaler is implemented in a low-cost commercial 0.18-μm SiGe BiCMOS technology. The maximum operating frequency is up to 10 GHz, with 8.6 mW power consumption in 1.8 V supply. The core area is 190 μm×120 μm. 2013-10-10T03:59:45Z 2019-12-06T20:44:22Z 2013-10-10T03:59:45Z 2019-12-06T20:44:22Z 2012 2012 Conference Paper Wang, K., Ma, K., & Yeo, K. S. (2012). Low-power high-speed dual-modulus prescaler for Gb/s applications. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.256-259. https://hdl.handle.net/10356/101771 http://hdl.handle.net/10220/16362 10.1109/APCCAS.2012.6419020 en
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Wang, Keping
Ma, Kaixue
Yeo, Kiat Seng
Low-power high-speed dual-modulus prescaler for Gb/s applications
description This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed and low power consumption simultaneously. The prescaler is implemented in a low-cost commercial 0.18-μm SiGe BiCMOS technology. The maximum operating frequency is up to 10 GHz, with 8.6 mW power consumption in 1.8 V supply. The core area is 190 μm×120 μm.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Wang, Keping
Ma, Kaixue
Yeo, Kiat Seng
format Conference or Workshop Item
author Wang, Keping
Ma, Kaixue
Yeo, Kiat Seng
author_sort Wang, Keping
title Low-power high-speed dual-modulus prescaler for Gb/s applications
title_short Low-power high-speed dual-modulus prescaler for Gb/s applications
title_full Low-power high-speed dual-modulus prescaler for Gb/s applications
title_fullStr Low-power high-speed dual-modulus prescaler for Gb/s applications
title_full_unstemmed Low-power high-speed dual-modulus prescaler for Gb/s applications
title_sort low-power high-speed dual-modulus prescaler for gb/s applications
publishDate 2013
url https://hdl.handle.net/10356/101771
http://hdl.handle.net/10220/16362
_version_ 1681044278207315968

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