A memory-efficient scalable architecture for lifting-based discrete wavelet transform
In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the f...
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sg-ntu-dr.10356-1024012020-03-07T14:00:33Z A memory-efficient scalable architecture for lifting-based discrete wavelet transform Hu, Yusong Jong, Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the flipped lifting algorithm, processing units (PUs) are developed for maximally utilizing the inherent parallelism. With S number of PUs, the throughput can be scaled while keeping the latency constant. Compared with the best existing architecture, the proposed architecture requires less memory. For an N × N image, the proposed architecture consumes a total of only 3N + 24S words of transposition memory, temporal memory, and pipeline registers. The synthesized results in a 90-nm CMOS process show that it achieves better area-delay products than the best existing design by 32.3%, 31.5%, and 27.0% when S = 2, 4, and 8, respectively, and by 26%, 26%, and 22% when the overhead for buffering the required overlapped pixels is taken into account. 2013-10-24T07:59:10Z 2019-12-06T20:54:19Z 2013-10-24T07:59:10Z 2019-12-06T20:54:19Z 2013 2013 Journal Article Hu, Y., & Jong, C. C. (2013). A memory-efficient scalable architecture for lifting-based discrete wavelet transform. IEEE transactions on circuits and systems II : express briefs, 60(8), 502-506. 1549-7747 https://hdl.handle.net/10356/102401 http://hdl.handle.net/10220/16815 10.1109/TCSII.2013.2268335 en IEEE transactions on circuits and systems II : express briefs |
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DRNTU::Engineering::Electrical and electronic engineering Hu, Yusong Jong, Ching Chuen A memory-efficient scalable architecture for lifting-based discrete wavelet transform |
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In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the flipped lifting algorithm, processing units (PUs) are developed for maximally utilizing the inherent parallelism. With S number of PUs, the throughput can be scaled while keeping the latency constant. Compared with the best existing architecture, the proposed architecture requires less memory. For an N × N image, the proposed architecture consumes a total of only 3N + 24S words of transposition memory, temporal memory, and pipeline registers. The synthesized results in a 90-nm CMOS process show that it achieves better area-delay products than the best existing design by 32.3%, 31.5%, and 27.0% when S = 2, 4, and 8, respectively, and by 26%, 26%, and 22% when the overhead for buffering the required overlapped pixels is taken into account. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Hu, Yusong Jong, Ching Chuen |
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Article |
author |
Hu, Yusong Jong, Ching Chuen |
author_sort |
Hu, Yusong |
title |
A memory-efficient scalable architecture for lifting-based discrete wavelet transform |
title_short |
A memory-efficient scalable architecture for lifting-based discrete wavelet transform |
title_full |
A memory-efficient scalable architecture for lifting-based discrete wavelet transform |
title_fullStr |
A memory-efficient scalable architecture for lifting-based discrete wavelet transform |
title_full_unstemmed |
A memory-efficient scalable architecture for lifting-based discrete wavelet transform |
title_sort |
memory-efficient scalable architecture for lifting-based discrete wavelet transform |
publishDate |
2013 |
url |
https://hdl.handle.net/10356/102401 http://hdl.handle.net/10220/16815 |
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1681046397966614528 |