A memory-efficient scalable architecture for lifting-based discrete wavelet transform

• Main Authors: Hu, Yusong, Jong, Ching Chuen
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2013
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/102401; http://hdl.handle.net/10220/16815
• 機構: Nanyang Technological University

In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the f...