A memory-efficient scalable architecture for lifting-based discrete wavelet transform

In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the f...

Full description

Saved in:
Bibliographic Details
Main Authors: Hu, Yusong, Jong, Ching Chuen
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2013
Subjects:
Online Access:https://hdl.handle.net/10356/102401
http://hdl.handle.net/10220/16815
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English