A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS
This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inv...
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| Main Authors: | , , |
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| Other Authors: | |
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2020
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/144421 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inverter chain is deployed as the delay unit with good linearity to increase the conversion rate and reduce the power consumption. In addition, dynamic logic is implemented to further improve the speed and energy efficiency. As a proof-of-concept design, the TDC is verified by post-layout simulation (Transient noise + Monte Carlo (MC)) in 40nm low power CMOS technology, achieving 0.98LSB /1.03LSB worst case differential nonlinearity (DNL)/integral nonlinearity (INL) and 0.014pJ/conversion-step figure-of-merit (FOM). The simulated single-shot precision (SSP) of the proposed TDC is 0.71 LSB. |
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