A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS

A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS

This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inv...

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書目詳細資料
Main Authors:	Chen, Qian, Liang, Yuan, Boon, Chirn Chye
其他作者:	School of Electrical and Electronic Engineering
格式:	Conference or Workshop Item
語言:	English
出版:	2020
主題:	Engineering::Electrical and electronic engineering ADC-based Wireline Dynamic Logic
在線閱讀:	https://hdl.handle.net/10356/144421
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!
機構:	Nanyang Technological University
語言:	English

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