A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS
This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inv...
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sg-ntu-dr.10356-1444212020-11-04T07:33:56Z A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS Chen, Qian Liang, Yuan Boon, Chirn Chye School of Electrical and Electronic Engineering 2020 IEEE International Symposium on Circuits and Systems (ISCAS) Engineering::Electrical and electronic engineering ADC-based Wireline Dynamic Logic This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inverter chain is deployed as the delay unit with good linearity to increase the conversion rate and reduce the power consumption. In addition, dynamic logic is implemented to further improve the speed and energy efficiency. As a proof-of-concept design, the TDC is verified by post-layout simulation (Transient noise + Monte Carlo (MC)) in 40nm low power CMOS technology, achieving 0.98LSB /1.03LSB worst case differential nonlinearity (DNL)/integral nonlinearity (INL) and 0.014pJ/conversion-step figure-of-merit (FOM). The simulated single-shot precision (SSP) of the proposed TDC is 0.71 LSB. Ministry of Education (MOE) Accepted version This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 (MOE2019-T2- 1-114). 2020-11-04T07:33:56Z 2020-11-04T07:33:56Z 2020 Conference Paper Chen, Q., Liang, Y., & Boon, C. C. (2020). A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS. Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/ISCAS45731.2020.9180949 2158-1525 https://hdl.handle.net/10356/144421 10.1109/ISCAS45731.2020.9180949 en MOE2019-T2- 1-114 © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work is available at: https://doi.org/10.1109/ISCAS45731.2020.9180949 application/pdf |
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Engineering::Electrical and electronic engineering ADC-based Wireline Dynamic Logic Chen, Qian Liang, Yuan Boon, Chirn Chye A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS |
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This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inverter chain is deployed as the delay unit with good linearity to increase the conversion rate and reduce the power consumption. In addition, dynamic logic is implemented to further improve the speed and energy efficiency. As a proof-of-concept design, the TDC is verified by post-layout simulation (Transient noise + Monte Carlo (MC)) in 40nm low power CMOS technology, achieving 0.98LSB /1.03LSB worst case differential nonlinearity (DNL)/integral nonlinearity (INL) and 0.014pJ/conversion-step figure-of-merit (FOM). The simulated single-shot precision (SSP) of the proposed TDC is 0.71 LSB. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Chen, Qian Liang, Yuan Boon, Chirn Chye |
format |
Conference or Workshop Item |
author |
Chen, Qian Liang, Yuan Boon, Chirn Chye |
author_sort |
Chen, Qian |
title |
A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS |
title_short |
A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS |
title_full |
A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS |
title_fullStr |
A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS |
title_full_unstemmed |
A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS |
title_sort |
6bit 1.2gs/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm cmos |
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2020 |
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https://hdl.handle.net/10356/144421 |
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1688665623160160256 |