A 6bit 1.2GS/s symmetric successive approximation energy-efficient time-to-digital converter in 40nm CMOS

• Main Authors: Chen, Qian, Liang, Yuan, Boon, Chirn Chye
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2020
• 主題: Engineering::Electrical and electronic engineering; ADC-based Wireline; Dynamic Logic
• 在線閱讀: https://hdl.handle.net/10356/144421
• 機構: Nanyang Technological University

This work presents a 6bit 1.2GS/s symmetric successive approximation (SSA) energy-efficient time-to-digital converter (TDC). The delay offset of the successive approximation (SA) TDC has been alleviated by employing the balanced architecture and optimizing the phase detector (PD). Size-optimized inv...