Fine pitch packaging study of CU or low-k devices

The main objective of this project is to improve and enhance the reliability performance of Cu / low-k flip chip ball grid array packages. This project is divided into three parts. The first part of the project involved developing an underfill selection methodology that enable researchers to screen...

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Main Author: Ong, Xuefen.
Other Authors: Chen Zhong
Format: Theses and Dissertations
Language:English
Published: 2009
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Online Access:http://hdl.handle.net/10356/14975
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-149752023-03-04T16:33:25Z Fine pitch packaging study of CU or low-k devices Ong, Xuefen. Chen Zhong School of Materials Science & Engineering DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects The main objective of this project is to improve and enhance the reliability performance of Cu / low-k flip chip ball grid array packages. This project is divided into three parts. The first part of the project involved developing an underfill selection methodology that enable researchers to screen away unfavourable candidates and chose the best underfills for their package through a series of reliability testing. The underfill selection methodology adopted in this project took into consideration of the overall underfill’s material properties, such as the fracture toughness, delamination performance, coefficient of moisture expansion, flowability and filler settlement. The driving stress or strain for failure at low-k layers and at solder bump corners were also included as one of the factor with the help of FEA modeling. Using this underfill selection methodology, we have managed to revise the underfill’s thermal properties range suitable for 15 x 15 mm2 flip chip packages, which will assist researchers in having a wider option in underfill selection for future FCBGA package. The second part of the project studied two types of interconnection schemes (i.e. 97.5Sn2.5Ag solder bumps and copper pillar interconnection). The reliability performance between these two interconnection scheme was compared using FEA modeling and through a series of reliability tests. EDX analysis was also conducted to examine the intermetallic compounds formed after reflow and after 1000 cycles of thermal cycling test. This work has enabled us to select more reliable interconnection scheme for future flip chip packages whereby the use of Pb in eutectic solder bumps is forbidden. In this section, we have demonstrated that copper pillar interconnection has better thermal mechanical performance than lead-free solder bumps, which can be considered as an option in replacing eutectic solder. The final part of the project focused on improving the package reliability performance by optimising certain package design parameters (i.e. dicing methods, die thickness and location of die pad). A set of parametric study have been carried out to evaluate the reliability performance between various parameters. By understanding the impact of these design parameters on package reliability has enabled us to further improve on flip chip package reliability. Master of Engineering (MSE) 2009-03-17T08:55:42Z 2009-03-17T08:55:42Z 2009 2009 Thesis http://hdl.handle.net/10356/14975 en 142 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
spellingShingle DRNTU::Engineering::Materials::Microelectronics and semiconductor materials::Nanoelectronics and interconnects
Ong, Xuefen.
Fine pitch packaging study of CU or low-k devices
description The main objective of this project is to improve and enhance the reliability performance of Cu / low-k flip chip ball grid array packages. This project is divided into three parts. The first part of the project involved developing an underfill selection methodology that enable researchers to screen away unfavourable candidates and chose the best underfills for their package through a series of reliability testing. The underfill selection methodology adopted in this project took into consideration of the overall underfill’s material properties, such as the fracture toughness, delamination performance, coefficient of moisture expansion, flowability and filler settlement. The driving stress or strain for failure at low-k layers and at solder bump corners were also included as one of the factor with the help of FEA modeling. Using this underfill selection methodology, we have managed to revise the underfill’s thermal properties range suitable for 15 x 15 mm2 flip chip packages, which will assist researchers in having a wider option in underfill selection for future FCBGA package. The second part of the project studied two types of interconnection schemes (i.e. 97.5Sn2.5Ag solder bumps and copper pillar interconnection). The reliability performance between these two interconnection scheme was compared using FEA modeling and through a series of reliability tests. EDX analysis was also conducted to examine the intermetallic compounds formed after reflow and after 1000 cycles of thermal cycling test. This work has enabled us to select more reliable interconnection scheme for future flip chip packages whereby the use of Pb in eutectic solder bumps is forbidden. In this section, we have demonstrated that copper pillar interconnection has better thermal mechanical performance than lead-free solder bumps, which can be considered as an option in replacing eutectic solder. The final part of the project focused on improving the package reliability performance by optimising certain package design parameters (i.e. dicing methods, die thickness and location of die pad). A set of parametric study have been carried out to evaluate the reliability performance between various parameters. By understanding the impact of these design parameters on package reliability has enabled us to further improve on flip chip package reliability.
author2 Chen Zhong
author_facet Chen Zhong
Ong, Xuefen.
format Theses and Dissertations
author Ong, Xuefen.
author_sort Ong, Xuefen.
title Fine pitch packaging study of CU or low-k devices
title_short Fine pitch packaging study of CU or low-k devices
title_full Fine pitch packaging study of CU or low-k devices
title_fullStr Fine pitch packaging study of CU or low-k devices
title_full_unstemmed Fine pitch packaging study of CU or low-k devices
title_sort fine pitch packaging study of cu or low-k devices
publishDate 2009
url http://hdl.handle.net/10356/14975
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