RF performance benchmarking of TSV integrated surface electrode ion trap for quantum computing

• Main Authors: Zhao, Peng, Li, Hong Yu, Tao, Jing, Likforman, Jean-Pierre, Lim, Yu Dian, Seit, Wen Wei, Luca, Guidoni, Tan, Chuan Seng
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Surface Electrode Ion Trap; Finite Element Modeling
• Online Access: https://hdl.handle.net/10356/153006
• Institution: Nanyang Technological University

Surface electrode ion trap is highly promising for practical quantum computing due to its superior controllability on the trapped ions. With advanced microfabrication techniques, silicon has been developed as ion trap substrate for delicate surface electrodes design as well as monolithic electro-optical components integration. However, the high RF loss of silicon hinders the possible large-scale implementation. In this work, we demonstrate a through silicon via (TSV) integrated ion trap, which has low RF loss due to the elimination of wire bonding pads on the surface and the miniaturization of form factor. We also fabricate two types of conventional wire bonding (WB) traps with or without a grounding screen layer. The RF performance of different ion traps are tested and compared, in terms of on-chip S-parameter, post-packaging resonance and resulting power loss. The results show that TSV trap has low S21 (~0.2 dB at 50 MHz), high Q factor (~22) and low power loss (0.26 W) as compared to WB traps. In addition, 3D finite element modelling is employed for electric field visualization and RF loss analysis of different traps. The extracted results from the modelling show a decent agreement with the measurements. In addition to various RF tests, the design, fabrication and ion trapping operation of different ion traps are presented. This work provides insights into RF loss of ion trapping device and offers a new solution for RF loss reduction.