A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS

A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS

A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capac...

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書目詳細資料
Main Authors: Jo, Yong-Jun, Kim, Ju Eon, Baek, Kwang-Hyun, Kim, Tony Tae-Hyoung
其他作者: School of Electrical and Electronic Engineering
格式: Article
語言:English
出版: 2021
主題:
Engineering::Electrical and electronic engineering::Integrated circuits
SAR ADC
Compute-in-Memory
在線閱讀:https://hdl.handle.net/10356/153185
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機構: Nanyang Technological University
語言: English
實物特徵
總結:A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98- μW, and FoM of 6.6-fJ/conv.-step.

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