Energy-efficient data-aware SRAM design utilizing column-based data encoding
This brief presents an ultra-low power SRAM utilizing a column-based data encoding scheme for power reduction. The proposed scheme is particularly beneficial in applications like bio-signal and image processing where neighboring data have similar values. The proposed technique generates write data t...
Saved in:
Main Authors: | Do, Anh Tuan, Seyed Mohammad Ali Zeinolabedin, Kim, Tony Tae-Hyoung |
---|---|
Other Authors: | School of Electrical and Electronic Engineering |
Format: | Article |
Language: | English |
Published: |
2022
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/155307 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement
by: Wang, Bo, et al.
Published: (2016) -
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization
by: Do, Anh Tuan, et al.
Published: (2016) -
Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing
by: Chen, Junchao, et al.
Published: (2016) -
An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS
by: Do, Anh Tuan, et al.
Published: (2020) -
An ultra-low-voltage VCO-based ΔΣ modulator using self-compensated current reference for variation tolerance
by: Narasimman, Neelakantan, et al.
Published: (2021)