ASIC implementation of a high speed and low power scalar product computation unit

• المؤلف الرئيسي: Low, Jeremy Yung Shern.
• مؤلفون آخرون: Chan Pak Kwong
• التنسيق: Final Year Project
• اللغة: English
• منشور في: 2009
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/16733

This project involves the design, synthesis and placement & routing of improved 16-bit 15-element unsigned inner product architecture. Improvement to the design were made in the carry free addition stage, which is also known as column compression stage or reduction stage, whereby counters are in...