Investigation of a modified NPN transistor in CMOS structures for enhanced ESD-induced latch-up protection

• 主要作者: Mo, Zhiyuan
• 其他作者: Poenar Daniel Puiu
• 格式: Thesis-Master by Coursework
• 語言: English
• 出版: Nanyang Technological University 2023
• 主題: Engineering::Electrical and electronic engineering::Semiconductors; Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: https://hdl.handle.net/10356/172084

Integrated circuits (ICs) are vital in modern electronics, including everyday life, industrial manufacturing and military equipment. Reducing transistor size and improving performance requires shrinking the gate oxide layer, which makes ICs more fragile and vulnerable to electrostatic discharg...