Investigation of a modified NPN transistor in CMOS structures for enhanced ESD-induced latch-up protection

• Main Author: Mo, Zhiyuan
• Other Authors: Poenar Daniel Puiu
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering::Semiconductors; Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/172084
• Institution: Nanyang Technological University

Integrated circuits (ICs) are vital in modern electronics, including everyday life, industrial manufacturing and military equipment. Reducing transistor size and improving performance requires shrinking the gate oxide layer, which makes ICs more fragile and vulnerable to electrostatic discharg...