Measurement of residual stress developed during advanced semiconductor packaging process

• Main Author: Huang, Guanbo.
• Other Authors: Zhong Zhaowei
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
• Online Access: http://hdl.handle.net/10356/17302
• Institution: Nanyang Technological University

This research report provides a focused investigation and theoretical review of thermal mismatch induced residual stress in semiconductor assembly and the application of utilizing piezoresistive stress sensor to conduct nondestructive measurement of such stress. In semiconductor fabrication process, these residual stresses are inevitable and capable of causing chip crack or delamination, thereby result in the loss of the chip functions as will as the damage of the package structure. Hence monitoring the residual stress plays an important role for determining the material suitable for the process and the critical process parameters. By embedding the piezoresistive stress sensor in the chip, residual stresses caused resistance shifts were recorded after die attachment process, chip encapsulation process, and several wafer level fabrication process such as UBM, solder bumping and dry film for 3 different silicon thicknesses (100um, 200um and 400um). Using the appropriate theoretical equations and the obtained piezoresistive coefficients, the residual stresses on the chip surface have been derived from the raw resistance data. Discussion deals with explaining the several critical stages of the residual stress development using some mechanical models. The measured residual stresses were plotted versus the chip thickness for die attachment process, chip encapsulation process. And it was found that the obtained trend matches with that derived from Stoney Equation using the bow measured from the silicon assembly.