Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors

This report presents the Design of Asynchronous Quasi-Delay-Insensitive Library Cells and Circuits for Asynchronous Microprocessors. Asynchronous are self-timed circuits that employ hand-shaking protocol. Quasi-Delay-Insensitive Library cells are circuits that do not assume any time delay to work pr...

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Main Author: Chin, Qi Lin.
Other Authors: Gwee Bah Hwee
Format: Final Year Project
Language:English
Published: 2009
Subjects:
Online Access:http://hdl.handle.net/10356/17314
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-173142023-07-07T16:23:36Z Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors Chin, Qi Lin. Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This report presents the Design of Asynchronous Quasi-Delay-Insensitive Library Cells and Circuits for Asynchronous Microprocessors. Asynchronous are self-timed circuits that employ hand-shaking protocol. Quasi-Delay-Insensitive Library cells are circuits that do not assume any time delay to work properly. These circuits can be used to communicate with asynchronous microprocessors. This library cells can be used by IC designers when designing bigger and more complex circuitry in future. The technology used is 0.13µm IBM technology. The Verilog/VHDL based individual cells (both single rail and double rail cells) are simulated in Synopsys Nanosim to verify the functionality of the circuit. The schematic of the designed circuit is designed in Cadence Virtuoso® Schematic Capture. A pre-layout simulation is performed in Cadence Virtuoso® Schematic Capture before proceeding to design the layout in Cadence Virtuoso® Layout Editing. After the layout is done, Design Rule Check (DRC) and Layout Versus Schematic (LVS) are performed to ensure that there are no design rule violations and the layout corresponds to the schematic using Mentor Graphics Calibre tool. Then, the parasitic capacitances of the cells are extracted using the same tool. Finally, a post-layout simulation is performed using Synopsys Nanosim to compare the results. The simulation results between pre-layout and post-layout have been compared. All the schematics and layouts of the circuits have been designed, simulated and verified. The functionality of all the library cells passed both the pre-layout and post-layout simulation. Bachelor of Engineering 2009-06-05T07:24:43Z 2009-06-05T07:24:43Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/17314 en Nanyang Technological University 279 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Chin, Qi Lin.
Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
description This report presents the Design of Asynchronous Quasi-Delay-Insensitive Library Cells and Circuits for Asynchronous Microprocessors. Asynchronous are self-timed circuits that employ hand-shaking protocol. Quasi-Delay-Insensitive Library cells are circuits that do not assume any time delay to work properly. These circuits can be used to communicate with asynchronous microprocessors. This library cells can be used by IC designers when designing bigger and more complex circuitry in future. The technology used is 0.13µm IBM technology. The Verilog/VHDL based individual cells (both single rail and double rail cells) are simulated in Synopsys Nanosim to verify the functionality of the circuit. The schematic of the designed circuit is designed in Cadence Virtuoso® Schematic Capture. A pre-layout simulation is performed in Cadence Virtuoso® Schematic Capture before proceeding to design the layout in Cadence Virtuoso® Layout Editing. After the layout is done, Design Rule Check (DRC) and Layout Versus Schematic (LVS) are performed to ensure that there are no design rule violations and the layout corresponds to the schematic using Mentor Graphics Calibre tool. Then, the parasitic capacitances of the cells are extracted using the same tool. Finally, a post-layout simulation is performed using Synopsys Nanosim to compare the results. The simulation results between pre-layout and post-layout have been compared. All the schematics and layouts of the circuits have been designed, simulated and verified. The functionality of all the library cells passed both the pre-layout and post-layout simulation.
author2 Gwee Bah Hwee
author_facet Gwee Bah Hwee
Chin, Qi Lin.
format Final Year Project
author Chin, Qi Lin.
author_sort Chin, Qi Lin.
title Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
title_short Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
title_full Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
title_fullStr Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
title_full_unstemmed Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
title_sort design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors
publishDate 2009
url http://hdl.handle.net/10356/17314
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