Design of asynchronous quasi-delay-insensitive library cells and circuits for asynchronous microprocessors

• 主要作者: Chin, Qi Lin.
• 其他作者: Gwee Bah Hwee
• 格式: Final Year Project
• 語言: English
• 出版: 2009
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• 在線閱讀: http://hdl.handle.net/10356/17314
• 機構: Nanyang Technological University

This report presents the Design of Asynchronous Quasi-Delay-Insensitive Library Cells and Circuits for Asynchronous Microprocessors. Asynchronous are self-timed circuits that employ hand-shaking protocol. Quasi-Delay-Insensitive Library cells are circuits that do not assume any time delay to work properly. These circuits can be used to communicate with asynchronous microprocessors. This library cells can be used by IC designers when designing bigger and more complex circuitry in future. The technology used is 0.13µm IBM technology. The Verilog/VHDL based individual cells (both single rail and double rail cells) are simulated in Synopsys Nanosim to verify the functionality of the circuit. The schematic of the designed circuit is designed in Cadence Virtuoso® Schematic Capture. A pre-layout simulation is performed in Cadence Virtuoso® Schematic Capture before proceeding to design the layout in Cadence Virtuoso® Layout Editing. After the layout is done, Design Rule Check (DRC) and Layout Versus Schematic (LVS) are performed to ensure that there are no design rule violations and the layout corresponds to the schematic using Mentor Graphics Calibre tool. Then, the parasitic capacitances of the cells are extracted using the same tool. Finally, a post-layout simulation is performed using Synopsys Nanosim to compare the results. The simulation results between pre-layout and post-layout have been compared. All the schematics and layouts of the circuits have been designed, simulated and verified. The functionality of all the library cells passed both the pre-layout and post-layout simulation.