Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU
This paper explores the utilization of hardware acceleration techniques for the non-linear layers in Transformer networks, specifically within the context of RISC-V CPU archi- tectures. The growing complexity of Transformer-based models, highlighted by their significant computational demands, unders...
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sg-ntu-dr.10356-1770932024-05-31T15:44:43Z Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU Seenivasagan Haresh Chang Chip Hong School of Electrical and Electronic Engineering ECHChang@ntu.edu.sg Engineering Hardware acceleration RISC-V Transformers This paper explores the utilization of hardware acceleration techniques for the non-linear layers in Transformer networks, specifically within the context of RISC-V CPU archi- tectures. The growing complexity of Transformer-based models, highlighted by their significant computational demands, underscores the need for optimized computing solu- tions. Despite the widespread application of these models in generating human-like text and other multi-modal AI tasks, their deployment is often hampered by the high volume of Floating Point Operations (FLOPs) required, particularly for activation functions like GELU, Softmax, and SiLU. RISC-V, an open Instruction Set Architecture (ISA), offers a promising avenue for addressing these challenges due to its customizable and royalty-free nature. This paper investigates the potential of RISC-V CPUs to provide efficient hard- ware acceleration for the computationally intensive layers of Transformer networks. By focusing on non-linear layers, we aim to enhance the overall execution speed and energy efficiency of these models . Bachelor's degree 2024-05-27T02:39:17Z 2024-05-27T02:39:17Z 2024 Final Year Project (FYP) Seenivasagan Haresh (2024). Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/177093 https://hdl.handle.net/10356/177093 en A2043-231 application/pdf Nanyang Technological University |
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Engineering Hardware acceleration RISC-V Transformers Seenivasagan Haresh Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU |
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This paper explores the utilization of hardware acceleration techniques for the non-linear layers in Transformer networks, specifically within the context of RISC-V CPU archi- tectures. The growing complexity of Transformer-based models, highlighted by their significant computational demands, underscores the need for optimized computing solu- tions. Despite the widespread application of these models in generating human-like text and other multi-modal AI tasks, their deployment is often hampered by the high volume of Floating Point Operations (FLOPs) required, particularly for activation functions like GELU, Softmax, and SiLU. RISC-V, an open Instruction Set Architecture (ISA), offers a promising avenue for addressing these challenges due to its customizable and royalty-free nature. This paper investigates the potential of RISC-V CPUs to provide efficient hard- ware acceleration for the computationally intensive layers of Transformer networks. By focusing on non-linear layers, we aim to enhance the overall execution speed and energy efficiency of these models . |
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Chang Chip Hong |
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Chang Chip Hong Seenivasagan Haresh |
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Final Year Project |
author |
Seenivasagan Haresh |
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Seenivasagan Haresh |
title |
Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU |
title_short |
Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU |
title_full |
Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU |
title_fullStr |
Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU |
title_full_unstemmed |
Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU |
title_sort |
hardware acceleration for non-linear layers of transformer networks on risc-v cpu |
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Nanyang Technological University |
publishDate |
2024 |
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https://hdl.handle.net/10356/177093 |
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1814047374256898048 |