High speed, low jitter CMOS analog PLL for clock recovery application

High speed, low jitter CMOS analog PLL for clock recovery application

This thesis presents a CMOS PLL differential design techniques for whole PLL systems in order to reject supply-coupled noise. Apart from the supply coupled noise, there are other issues in the PLL systems such as closed loop bandwidth requirements, reduction of the VCO phase noise through appropriat...

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Main Author: Sudhaleswar Behera.
Other Authors: Zhang, Yue Ping
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:http://hdl.handle.net/10356/3294
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Institution: Nanyang Technological University
id sg-ntu-dr.10356-3294
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spelling sg-ntu-dr.10356-32942023-07-04T15:52:17Z High speed, low jitter CMOS analog PLL for clock recovery application Sudhaleswar Behera. Zhang, Yue Ping School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits This thesis presents a CMOS PLL differential design techniques for whole PLL systems in order to reject supply-coupled noise. Apart from the supply coupled noise, there are other issues in the PLL systems such as closed loop bandwidth requirements, reduction of the VCO phase noise through appropriate topologies, dead zone elimination in PFD and reduction of charge sharing and clock feed through in Charge Pump. This thesis discusses all the issues briefly and applies same methodologies to the above design. Moreover, since this PLL uses differential structure, and hence works at reduced voltage swing, it is not only has the potential of operating at high frequency but also dissipate less power. Master of Science (Microelectronics) 2008-09-17T09:26:41Z 2008-09-17T09:26:41Z 2003 2003 Thesis http://hdl.handle.net/10356/3294 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Sudhaleswar Behera.
High speed, low jitter CMOS analog PLL for clock recovery application
description This thesis presents a CMOS PLL differential design techniques for whole PLL systems in order to reject supply-coupled noise. Apart from the supply coupled noise, there are other issues in the PLL systems such as closed loop bandwidth requirements, reduction of the VCO phase noise through appropriate topologies, dead zone elimination in PFD and reduction of charge sharing and clock feed through in Charge Pump. This thesis discusses all the issues briefly and applies same methodologies to the above design. Moreover, since this PLL uses differential structure, and hence works at reduced voltage swing, it is not only has the potential of operating at high frequency but also dissipate less power.
author2 Zhang, Yue Ping
author_facet Zhang, Yue Ping
Sudhaleswar Behera.
format Theses and Dissertations
author Sudhaleswar Behera.
author_sort Sudhaleswar Behera.
title High speed, low jitter CMOS analog PLL for clock recovery application
title_short High speed, low jitter CMOS analog PLL for clock recovery application
title_full High speed, low jitter CMOS analog PLL for clock recovery application
title_fullStr High speed, low jitter CMOS analog PLL for clock recovery application
title_full_unstemmed High speed, low jitter CMOS analog PLL for clock recovery application
title_sort high speed, low jitter cmos analog pll for clock recovery application
publishDate 2008
url http://hdl.handle.net/10356/3294
_version_ 1772827657233235968

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