High speed, low jitter CMOS analog PLL for clock recovery application

• 主要作者: Sudhaleswar Behera.
• 其他作者: Zhang, Yue Ping
• 格式: Theses and Dissertations
• 出版: 2008
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: http://hdl.handle.net/10356/3294

This thesis presents a CMOS PLL differential design techniques for whole PLL systems in order to reject supply-coupled noise. Apart from the supply coupled noise, there are other issues in the PLL systems such as closed loop bandwidth requirements, reduction of the VCO phase noise through appropriat...