High speed, low jitter CMOS analog PLL for clock recovery application

• Main Author: Sudhaleswar Behera.
• Other Authors: Zhang, Yue Ping
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/3294
• Institution: Nanyang Technological University

This thesis presents a CMOS PLL differential design techniques for whole PLL systems in order to reject supply-coupled noise. Apart from the supply coupled noise, there are other issues in the PLL systems such as closed loop bandwidth requirements, reduction of the VCO phase noise through appropriat...