Characterization and modeling of on-wafer interconnects for RFICs

• Main Author: Shi, Xiaomeng
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
• Online Access: https://hdl.handle.net/10356/3506
• Institution: Nanyang Technological University

This thesis addresses the characterization and modeling of on-wafer interconnects for CMOS RFICs. A scalable equivalent circuit model for complex-shaped interconnects is proposed. In this proposed structure, frequency-variant characteristics are modeled by frequency independent components. Therefore, the proposed model is compatible with commercial electronic design automation (EDA) tools. The accuracy of the model is verified with on-wafer measurements. Moreover, the proposed model is employed in the post-layout simulation of a real circuit. The simulated and measured figures of merit (FoM) of the circuit are compared and analyzed. The proposed model demonstrates higher accuracy than the foundry provided model. Also addressed in this thesis is the sensitivities of interconnects to CMOS process parameters.