Enhanced low-power high-speed probabilistic adders for error-toerant application

In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. To overcome all the possible errors is a very expensive task. It not only consumes a lot of power but also degrades the speed performance. With the concept of “error-tolerant” (ET), which allows the existence of...

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Main Author: Zhu, Ning
Other Authors: Goh Wang Ling
Format: Theses and Dissertations
Language:English
Published: 2011
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Online Access:https://hdl.handle.net/10356/46273
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-462732023-07-04T17:38:30Z Enhanced low-power high-speed probabilistic adders for error-toerant application Zhu, Ning Goh Wang Ling School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. To overcome all the possible errors is a very expensive task. It not only consumes a lot of power but also degrades the speed performance. With the concept of “error-tolerant” (ET), which allows the existence of certain amount of errors, improvements in power consumption and/or other performance metrics can be achieved. In this design, the concept of error-tolerant has been extended to the field of circuit design. When “imperfect” algorithms and circuit structures are employed, a substantial yield for an error-tolerant digital circuit, in terms of power consumption, speed performance, and transistor count, can be realized. An adder is the basic digital circuit component, which is widely used in many areas. Adopting the ideas and techniques in Error-Tolerant technology in the design of digital adders, a innovative type of adder—Probabilistic Adder for Error-Tolerant Application (ETA) has been designed. In conventional design, obtaining high speed usually means more power will be consumed and low power will normally degrade the speed of a circuit. To breakthrough this bottleneck in conventional technologies for designing a truly low-power and high-speed digital circuit, a new metric besides power and speed should be brought into the design process. In the proposed designs, accuracy plays the role of such a new metric. By sacrificing some degree of accuracy, great improvements in both power consumption and speed performance can be achieved. Several different implementations of the enhanced ETA have been proposed in the report, namely the ETA Type II (ETAII), ETA Type III (ETAIII) and ETA Type IV (ETAIV). The ETAII is based on the idea that in most cases the carry signal for a bit position is determined by several neighboring bits instead of all the bits on its right. Hence, the critical path of the whole circuit can be greatly curtailed by dividing the whole adder into a number of blocks and conducting the addition operations in each block concurrently. MASTER OF ENGINEERING (EEE) 2011-11-28T01:53:03Z 2011-11-28T01:53:03Z 2011 2011 Thesis Zhu, N. (2011). Enhanced low-power high-speed probabilistic adders for error-toerant application. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/46273 10.32657/10356/46273 en 98 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Zhu, Ning
Enhanced low-power high-speed probabilistic adders for error-toerant application
description In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. To overcome all the possible errors is a very expensive task. It not only consumes a lot of power but also degrades the speed performance. With the concept of “error-tolerant” (ET), which allows the existence of certain amount of errors, improvements in power consumption and/or other performance metrics can be achieved. In this design, the concept of error-tolerant has been extended to the field of circuit design. When “imperfect” algorithms and circuit structures are employed, a substantial yield for an error-tolerant digital circuit, in terms of power consumption, speed performance, and transistor count, can be realized. An adder is the basic digital circuit component, which is widely used in many areas. Adopting the ideas and techniques in Error-Tolerant technology in the design of digital adders, a innovative type of adder—Probabilistic Adder for Error-Tolerant Application (ETA) has been designed. In conventional design, obtaining high speed usually means more power will be consumed and low power will normally degrade the speed of a circuit. To breakthrough this bottleneck in conventional technologies for designing a truly low-power and high-speed digital circuit, a new metric besides power and speed should be brought into the design process. In the proposed designs, accuracy plays the role of such a new metric. By sacrificing some degree of accuracy, great improvements in both power consumption and speed performance can be achieved. Several different implementations of the enhanced ETA have been proposed in the report, namely the ETA Type II (ETAII), ETA Type III (ETAIII) and ETA Type IV (ETAIV). The ETAII is based on the idea that in most cases the carry signal for a bit position is determined by several neighboring bits instead of all the bits on its right. Hence, the critical path of the whole circuit can be greatly curtailed by dividing the whole adder into a number of blocks and conducting the addition operations in each block concurrently.
author2 Goh Wang Ling
author_facet Goh Wang Ling
Zhu, Ning
format Theses and Dissertations
author Zhu, Ning
author_sort Zhu, Ning
title Enhanced low-power high-speed probabilistic adders for error-toerant application
title_short Enhanced low-power high-speed probabilistic adders for error-toerant application
title_full Enhanced low-power high-speed probabilistic adders for error-toerant application
title_fullStr Enhanced low-power high-speed probabilistic adders for error-toerant application
title_full_unstemmed Enhanced low-power high-speed probabilistic adders for error-toerant application
title_sort enhanced low-power high-speed probabilistic adders for error-toerant application
publishDate 2011
url https://hdl.handle.net/10356/46273
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