Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)

This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional...

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Bibliographic Details
Main Author:	Low, Hong Guan.
Other Authors:	Koh, Liang Mong
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
Online Access:	http://hdl.handle.net/10356/4811
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-4811
record_format	dspace
spelling	sg-ntu-dr.10356-48112023-07-04T16:01:46Z Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP) Low, Hong Guan. Koh, Liang Mong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Microelectronics This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional and advanced packages. Master of Science (Microelectronics) 2008-09-17T09:59:10Z 2008-09-17T09:59:10Z 2003 2003 Thesis http://hdl.handle.net/10356/4811 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Microelectronics Low, Hong Guan. Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)
description	This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional and advanced packages.
author2	Koh, Liang Mong
author_facet	Koh, Liang Mong Low, Hong Guan.
format	Theses and Dissertations
author	Low, Hong Guan.
author_sort	Low, Hong Guan.
title	Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)
title_short	Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)
title_full	Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)
title_fullStr	Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)
title_full_unstemmed	Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)
title_sort	electrical design, modelling and optimization of a low-cost wafer level chip scale package (wl-csp)
publishDate	2008
url	http://hdl.handle.net/10356/4811
_version_	1772828281668632576

Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)

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