Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)

• Main Author: Low, Hong Guan.
• Other Authors: Koh, Liang Mong
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• Online Access: http://hdl.handle.net/10356/4811
• Institution: Nanyang Technological University

This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional...