Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)

Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)

This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional...

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書目詳細資料
主要作者:	Low, Hong Guan.
其他作者:	Koh, Liang Mong
格式:	Theses and Dissertations
出版:	2008
主題:	DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
在線閱讀:	http://hdl.handle.net/10356/4811
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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