Electrical design, modelling and optimization of a low-cost wafer level chip scale package (WL-CSP)

• 主要作者: Low, Hong Guan.
• 其他作者: Koh, Liang Mong
• 格式: Theses and Dissertations
• 出版: 2008
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• 在線閱讀: http://hdl.handle.net/10356/4811
• 機構: Nanyang Technological University

This report presented the design of a Wafer Level Chip-Scale Package (WL-CSP) using a patented UTAC’s Build Up (UBU) technology, which is a low-cost packaging process with a redistribution layer. From various papers, it had been shown that WL-CSP has superior electrical performance over conventional...