Electrical characterization of bias temperature instability in MOSFETs with the ultrathin SiON and la-doped HfSiO gate dielectrics

• Main Author: Du, Guoan.
• Other Authors: Ang Diing Shenp
• Format: Theses and Dissertations
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Microelectronics
• Online Access: http://hdl.handle.net/10356/51195
• Institution: Nanyang Technological University

The initial stage of the project involved the development of a new ultra-fast switching (UFS) method for the measurement of the bias temperature instability (BTI) phenomenon in state-of-the-art MOSFETs. This is followed by a systematic and detailed investigation on the negative-bias temperature instability (NBTI) of the ultrathin oxynitride (SiON) gate p-MOSFET and the BTI of the Hafnium silicate (HfSiO) gate MOSFETs. UFS method with 40ns measurement capability is developed to capture fast recovery component of BTI induced degradation. The working principle of the method is to apply voltage pulse on gate and capture the corresponding current pulse value. UFS formulas which convert measurement raw data into the MOSFET performance parameter degradation (|DVt|) are derived and shown clearly. As a new measurement method, UFS has been proved as a valid measurement technique for state of art MOSFETs. The minimum measurement time of UFS can be as short as 40 ns, which is one of the fastest measurement methods for BTI characterization. The extremely short measurement time minimizes the impact of the well-known fast recovery behavior of BTI, hence provides a more accurate value to indicate the real BTI degradation. Comparing with conventional slow IdVg measurement, UFS shows capability to capture large amount of fast recovery component. Hence, the newly developed UFS can provide a new insight of BTI degradation/ recovery mechanism. A detailed investigation of the NBTI induced degradation of the ultrathin SiON p-MOSFET is carried out with UFS measurement. Experimental data shows fast hole traps are generated gradually within 1s and saturated after 1s when the device is stressed under high electric field stress at elevated temperature. The total amount of saturated fast hole traps has strong dependency on gate stress voltage and stress temperature. With the charge pumping and conventional IdVg measurements, the data proves that the energy distribution of stress induced positive interface trapped charge is relatively broad, extending above the middle of the Si bandgap. This phenomenological explanation agrees with the findings of a first-principle simulation study on E'δ centers. Then, a new physical framework based on E' centers theory is proposed to explain the threshold degradation of p-MOSFET under negative-bias temperature stress. The shallow E'δ centers (90% in entire E' centers) are the dominant structures for the fast hole traps. Under certain stress voltage and temperature, the number of E'δ centers is saturated because the reaction of pre-existing oxygen vacancies at shallow regime reaches its dynamic balance. On the other hand, lengthening of the stress time allows the generation of deeper hole trap states arising greater structural relaxation through increased interaction with lattice phonons. The relatively deep level E'γ4 configurations are responsible for slow interfacial trapped charges. The bipolar nature of interfacial trapped charges can be explained physically with E'γ4 configurations, which has three phases, hole traps, neutral dipole, and electron traps.