New architectures of multiplier and inner-product processor for high-speed on-chip serial-link bus

• Main Author: Meher, Manas Ranjan.
• Other Authors: Jong Ching Chuen
• Format: Theses and Dissertations
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits; DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/52489
• Institution: Nanyang Technological University

Research activities in bit-serial arithmetic circuits have been saturated in recent years due to the unprecedented throughput demand in today's electronic applications that is difficult to achieve even by the parallel counterparts. In addition, the area advantage of serial architecture is becoming insignificant due to technology scaling. However, with the rapid increase in integration density of Intellectual Properties (IPs) and application modules in a single System-on-Chip (SoC) to cater for a wide range of applications, the on-chip parallel communication has been severely affected due to routing complexity and power dissipation of interconnects. To eliminate this problem, recent attempts have been made to reduce the number of on-chip parallel channels by introducing the serial-link bus architecture. The serial-link bus architecture establishes bit-serial communication among the on-chip modules at several Giga bits per second (Gbps). With this new approach, serial architectures could find a new set of applications if they are able to process the data at ultra high frequency. The primary goal of this work is to investigate the bit serial implementation of commonly used arithmetic circuits such as accumulator, multiplier and multiply-and-accumulate (MAC) units capable of directly sampling and processing serial-link data at Gbps without buffering. The thesis presents a novel approach that utilizes simple binary counters in designing accumulators, multipliers, inner-product units and discrete cosine transform (DCT) processors. The conventional full adder (FA) used in these circuits are functionally replaced by 1's counter circuit to significantly boost up the sampling frequency of these bit-serial arithmetic circuits.