Timing mismatch calibration circuit for high-speed time-interleaved ADCs

Timing mismatch calibration circuit for high-speed time-interleaved ADCs

The concept of a Time-Interleaved analog-to-digital converter (TI ADC) which comprises sub-ADCs (channels) is proposed as a means of increasing the speed of analog-to-digital converters (ADCs), albeit with a power and area penalty. During the alternate sampling process, timing mismatch between th...

Saved in:

書目詳細資料
主要作者:	Liu, Yifei
其他作者:	Chang Joseph Sylvester
格式:	Theses and Dissertations
語言:	English
出版:	2018
主題:	DRNTU::Engineering::Electrical and electronic engineering
在線閱讀:	http://hdl.handle.net/10356/76014
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

相似書籍

Timing mismatch calibration circuit for high-speed time-interleaved ADC
由: Seow, Yue Han
出版: (2019)

Timing mismatch calibration for time- interleaved ADC
由: Tan, Clarice Wen Ying
出版: (2019)

Digital timing mismatch detection and calibration for high-speed time interleaved ADC
由: Ho, Raymond
出版: (2020)

Design of frequency-interleaved ADC with mismatch compensation
由: Qiu, L., et al.
出版: (2014)

A digital time skew calibration technique for time-interleaved ADCs
由: Qiu, Lei, et al.
出版: (2016)

Time-interleaved SAR ADC with background timing-skew calibration for UWB wireless communication in IoT systems
由: Seong, Kiho, et al.
出版: (2020)

High-speed CMOS time-domain ADC design
由: Chen, Qian
出版: (2023)

Time-interleaved analog-to-digital converter mismatch compensation using infinite impulse response filters
由: Xu, Saihua
出版: (2016)

High speed ADC
由: Lin, Esmond Chengyuan
出版: (2017)

High-Speed ADC
由: Lu, Qian Qian
出版: (2015)

High-speed CMOS pipelined subranging ADC
由: Fan, Xianping
出版: (2010)

Evaluation program for high speed ADC
由: Lu, Yu Wen.
出版: (2010)

Design of high performance continuous time sigma delta ADC
由: Zhang, Fan
出版: (2011)

Interface design of high speed ADC based on FPGA
由: Li, Ziyi
出版: (2023)

A high-speed 2-bit/cycle SAR ADC with time-domain quantization
由: Qiu, Lei, et al.
出版: (2020)

Design of high speed high resolution ADC with innovative architecture and circuits
由: Qiu, Lei
出版: (2016)

K-locked-loop and its application in time mode ADC
由: Hor, Hon Cheong, et al.
出版: (2010)

Source follower-based high-speed switched capacitor amplifier for pipelined ADCs
由: Siek, Liter, et al.
出版: (2015)

High-speed spoof plasmonic circuit
由: Qiu, Liangdong
出版: (2023)

Time- and wavelength-interleaved optical pulse train generation based on dispersion spreading and sectional compression
由: Lam, Huy Quoc, et al.
出版: (2013)

Study of power supply design for high speed circuit
由: Toh, Tze Yan.
出版: (2010)

Robust control of nonlinear time-varying mismatched uncertain systems
由: Wang, Wei Hua.
出版: (2010)

Development of an advanced nano-satellite VELOX-I – study of column-level ADC architectures for high speed CMOS image sensors
由: Liu, Lifen.
出版: (2013)

An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
由: Jiang, Shan, et al.
出版: (2010)

Self-timed CMOS circuits
由: Lakshminarayanan Srinivasan
出版: (2008)

Feasibility studies of high data rate ADC
由: Goo, Yong Soon.
出版: (2009)

Impacts of EMI filter on high speed interconnects for digital circuits design
由: Chang, Richard Weng Yew, et al.
出版: (2013)

Design of wire bond inductors and high-speed printed circuit board
由: Mohamed Mansoor Mohamed Mafraz
出版: (2017)

Sample-and-hold circuits for ultra-high-speed analog-to-digital converters
由: Huang, Jiong.
出版: (2013)

Design of high-speed low-power clock and data recovery circuit
由: Alper, Cabuk
出版: (2008)

Design of switching trigger circuit of SAR logic controller for Radix-3 system SAR ADC
由: Abdussalam, Mohamad Ichiko
出版: (2015)

CMOS differential logic circuits for low power and high-speed applications
由: They, Kian Seng
出版: (2008)

Design of high speed advanced encryption standard (AES) encryption circuit
由: Li, Lantian
出版: (2022)

A 98.6 dB SNDR SAR ADC with a mismatch error shaping technique implemented with double sampling
由: Yang, Chuanshi, et al.
出版: (2022)

Intelligent precision indoor real time location system : calibration algorithms
由: Sze Toh, Melvin Yong Kang
出版: (2021)

A current-mode stimulator circuit with two-step charge balancing background calibration
由: Xiong, Gordon M., et al.
出版: (2013)

ADC high speed data streaming for the UAV-borne radar system
由: New, Dominic Mun Keat
出版: (2016)

Low-power high-performance SAR ADC with redundancy and digital error-correction
由: Sharma, Sunny
出版: (2018)

Highly lattice-mismatched epitaxy for III-V/Si integration
由: Jia, Bowen
出版: (2018)

Effect of nonlinear inductor behavior on the performance of interleaved power factor correction
由: Liu, Yitao., et al.
出版: (2013)