A 0.058 mm2 24 µw temperature sensor in 40 nm cmos process with ± 0.5 ◦c inaccuracy from −55 to 175 ◦c
This paper describes the design of a high-accuracy smart temperature sensor in the 40 nm standard CMOS process. Due to process scaling, the high threshold voltages, large leakage currents and low intrinsic gains, etc., cause the realization of conventional high performance analog circuits to become...
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| Main Authors: | , |
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| Other Authors: | |
| Format: | Article |
| Language: | English |
| Published: |
2019
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/85863 http://hdl.handle.net/10220/48291 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This paper describes the design of a high-accuracy smart temperature sensor in the 40 nm standard CMOS process. Due to process scaling, the high threshold voltages, large leakage currents and low intrinsic gains, etc., cause the realization of conventional high performance analog circuits to become very challenging in advanced processes. In the proposed design, some new techniques have been utilized in order to overcome the obstacles due to process scaling. The sensor’s frontend is based on substrate PNP transistors, couple with a two-step zooming ADC. This temperature sensor achieves a two-point calibrated inaccuracy of ± 0.5 ◦C and a one-point trimmed inaccuracy of± 0.8 ◦C over a range of temperature from−55 to 175 ◦C. It draws 20 µA from a 1.2 V power supply and occupies an area of 0.0578 mm2. |
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