A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET

A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET

Recent device reliability studies have observed the shallow-to-deep transformation of electron-trap states under positive-bias temperature stressing. Being two typical types of defects in the high-κ oxide, the oxygen vacancy and oxygen interstitial have been investigated in many simulations, but res...

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Main Authors: Gu, Chenjie, Ang, Diing Shenp, Gao, Yuan, Gu, Renyuan, Zhao, Ziqi, Zhu, Chao
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2018
Subjects:
CMOS Reliability
Dynamic Bias Temperature Instability (BTI)
Online Access:https://hdl.handle.net/10356/86839
http://hdl.handle.net/10220/45202
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-868392020-03-07T13:57:30Z A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET Gu, Chenjie Ang, Diing Shenp Gao, Yuan Gu, Renyuan Zhao, Ziqi Zhu, Chao School of Electrical and Electronic Engineering CMOS Reliability Dynamic Bias Temperature Instability (BTI) Recent device reliability studies have observed the shallow-to-deep transformation of electron-trap states under positive-bias temperature stressing. Being two typical types of defects in the high-κ oxide, the oxygen vacancy and oxygen interstitial have been investigated in many simulations, but results have indicated that the corresponding defect levels are either too shallow or too deep and fail to explain the experimental observation. Here, we propose a vacancy-interstitial (V o -O i ) model. By tuning the relative positions of V o and O i , we show that the charge trap level of the defect pair can be adjusted continuously within the HfO 2 bandgap. This allows us to depict a possible atomic picture for understanding the shallow-to-deep transformation of electron trapping. MOE (Min. of Education, S’pore) 2018-07-24T03:49:35Z 2019-12-06T16:29:59Z 2018-07-24T03:49:35Z 2019-12-06T16:29:59Z 2017 Journal Article Gu, C., Ang, D. S., Gao, Y., Gu, R., Zhao, Z., & Zhu, C. (2017). A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET. IEEE Transactions on Electron Devices, 64(6), 2505-2511. 0018-9383 https://hdl.handle.net/10356/86839 http://hdl.handle.net/10220/45202 10.1109/TED.2017.2694440 en IEEE Transactions on Electron Devices © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/TED.2017.2694440]. 7 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic CMOS Reliability
Dynamic Bias Temperature Instability (BTI)
spellingShingle CMOS Reliability
Dynamic Bias Temperature Instability (BTI)
Gu, Chenjie
Ang, Diing Shenp
Gao, Yuan
Gu, Renyuan
Zhao, Ziqi
Zhu, Chao
A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET
description Recent device reliability studies have observed the shallow-to-deep transformation of electron-trap states under positive-bias temperature stressing. Being two typical types of defects in the high-κ oxide, the oxygen vacancy and oxygen interstitial have been investigated in many simulations, but results have indicated that the corresponding defect levels are either too shallow or too deep and fail to explain the experimental observation. Here, we propose a vacancy-interstitial (V o -O i ) model. By tuning the relative positions of V o and O i , we show that the charge trap level of the defect pair can be adjusted continuously within the HfO 2 bandgap. This allows us to depict a possible atomic picture for understanding the shallow-to-deep transformation of electron trapping.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Gu, Chenjie
Ang, Diing Shenp
Gao, Yuan
Gu, Renyuan
Zhao, Ziqi
Zhu, Chao
format Article
author Gu, Chenjie
Ang, Diing Shenp
Gao, Yuan
Gu, Renyuan
Zhao, Ziqi
Zhu, Chao
author_sort Gu, Chenjie
title A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET
title_short A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET
title_full A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET
title_fullStr A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET
title_full_unstemmed A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET
title_sort vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-mosfet
publishDate 2018
url https://hdl.handle.net/10356/86839
http://hdl.handle.net/10220/45202
_version_ 1681043358188830720

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