Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel
We have fabricated silicon nanowire N-MOSFETs using erbium disilicide (ErSi2−x) in a Schottky source/drain back-gated architecture. Although the subthreshold swing (~180 mV/dec) and drain-induced barrier lowering (~500 mV/V) are high due thick BOX as gate oxide, the fabricated Schottky t...
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2012
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sg-ntu-dr.10356-905762023-07-14T15:46:00Z Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel Cui, Guangda Lee, Pooi See Chi, Dong Zhi Chin, Yoke King Hoe, Keat Mun Tan, Eu Jin Pey, Kin Leong Singh, Navab Lo, Guo-Qiang School of Materials Science & Engineering DRNTU::Engineering::Materials We have fabricated silicon nanowire N-MOSFETs using erbium disilicide (ErSi2−x) in a Schottky source/drain back-gated architecture. Although the subthreshold swing (~180 mV/dec) and drain-induced barrier lowering (~500 mV/V) are high due thick BOX as gate oxide, the fabricated Schottky transistors show acceptable drive current ~900 μA/μm and high Ion/Ioff ratio (~105). This is attributed to the improved carrier injection as a result of low Schottky barrier height (Φb) of ErSi2−x/n − Si(~0.3 eV) and the nanometer-sized (~8 nm) Schottky junction. The carrier transport is found to be dominated by the metal–semiconductor interface instead of the channel body speculated from the channel length independent behavior of the devices. Furthermore, the transistors exhibit ambipolar characteristics, which are modeled using thermionic/ thermionic-field emission for positive and thermionic-field emission for negative gate biases. Accepted version 2012-07-26T03:51:17Z 2019-12-06T17:50:10Z 2012-07-26T03:51:17Z 2019-12-06T17:50:10Z 2008 2008 Journal Article Tan, E. J., Pey, K. L., Singh, N., Lo, G., Q., Chi, D. Z., Chin, Y. K., et al. (2008). Demonstration of Schottky Barrier NMOS Transistors with Erbium Silicided Source/drain and Silicon Nanowire Channel. IEEE Electron Device Letters, 29(10), 1167-1170. https://hdl.handle.net/10356/90576 http://hdl.handle.net/10220/8343 10.1109/LED.2008.2004508 en IEEE electron device letters © 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: http://dx.doi.org/10.1109/LED.2008.2004508. application/pdf |
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DRNTU::Engineering::Materials Cui, Guangda Lee, Pooi See Chi, Dong Zhi Chin, Yoke King Hoe, Keat Mun Tan, Eu Jin Pey, Kin Leong Singh, Navab Lo, Guo-Qiang Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel |
| description |
We have fabricated silicon nanowire N-MOSFETs using erbium disilicide (ErSi2−x) in a Schottky source/drain
back-gated architecture. Although the subthreshold swing
(~180 mV/dec) and drain-induced barrier lowering (~500 mV/V)
are high due thick BOX as gate oxide, the fabricated
Schottky transistors show acceptable drive current ~900 μA/μm
and high Ion/Ioff ratio (~105). This is attributed to the improved
carrier injection as a result of low Schottky barrier height
(Φb) of ErSi2−x/n − Si(~0.3 eV) and the nanometer-sized
(~8 nm) Schottky junction. The carrier transport is found to be
dominated by the metal–semiconductor interface instead of the
channel body speculated from the channel length independent
behavior of the devices. Furthermore, the transistors exhibit
ambipolar characteristics, which are modeled using thermionic/
thermionic-field emission for positive and thermionic-field
emission for negative gate biases. |
| author2 |
School of Materials Science & Engineering |
| author_facet |
School of Materials Science & Engineering Cui, Guangda Lee, Pooi See Chi, Dong Zhi Chin, Yoke King Hoe, Keat Mun Tan, Eu Jin Pey, Kin Leong Singh, Navab Lo, Guo-Qiang |
| format |
Article |
| author |
Cui, Guangda Lee, Pooi See Chi, Dong Zhi Chin, Yoke King Hoe, Keat Mun Tan, Eu Jin Pey, Kin Leong Singh, Navab Lo, Guo-Qiang |
| author_sort |
Cui, Guangda |
| title |
Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel |
| title_short |
Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel |
| title_full |
Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel |
| title_fullStr |
Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel |
| title_full_unstemmed |
Demonstration of Schottky barrier NMOS transistors with erbium silicided source/drain and silicon nanowire channel |
| title_sort |
demonstration of schottky barrier nmos transistors with erbium silicided source/drain and silicon nanowire channel |
| publishDate |
2012 |
| url |
https://hdl.handle.net/10356/90576 http://hdl.handle.net/10220/8343 |
| _version_ |
1772827202552856576 |