Statistical modeling of via redundancy effects on interconnect reliability

Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach i...

وصف كامل

محفوظ في:
التفاصيل البيبلوغرافية
المؤلفون الرئيسيون: Tan, Cher Ming, Raghavan, Nagarajan
مؤلفون آخرون: School of Electrical and Electronic Engineering
التنسيق: Conference or Workshop Item
اللغة:English
منشور في: 2010
الموضوعات:
الوصول للمادة أونلاين:https://hdl.handle.net/10356/90793
http://hdl.handle.net/10220/6345
الوسوم: إضافة وسم
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المؤسسة: Nanyang Technological University
اللغة: English
الوصف
الملخص:Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach is to have an in-built redundancy in the via structures of the interconnect. The presence of redundant via in a parallel topology helps improve the overall reliability of the via structure. Although reliability improvement due to via redundancy is qualitatively understood, it is necessary to quantify the improvement in reliability through statistical models so that the improvement in lifetime as a result of redundancy can be quantified. A statistical model that incorporates the effects of redundancy is developed in this study and it is used to estimate the reliability of redundant via structures. The Cumulative Damage Model (CDM) is used in conjunction with the Maximum Likelihood Estimate (MLE) method to assess the reliability of load sharing via redundant structures in this study.