Statistical modeling of via redundancy effects on interconnect reliability

• Main Authors: Tan, Cher Ming, Raghavan, Nagarajan
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/90793; http://hdl.handle.net/10220/6345
• Institution: Nanyang Technological University

Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach is to have an in-built redundancy in the via structures of the interconnect. The presence of redundant via in a parallel topology helps improve the overall reliability of the via structure. Although reliability improvement due to via redundancy is qualitatively understood, it is necessary to quantify the improvement in reliability through statistical models so that the improvement in lifetime as a result of redundancy can be quantified. A statistical model that incorporates the effects of redundancy is developed in this study and it is used to estimate the reliability of redundant via structures. The Cumulative Damage Model (CDM) is used in conjunction with the Maximum Likelihood Estimate (MLE) method to assess the reliability of load sharing via redundant structures in this study.