Statistical modeling of via redundancy effects on interconnect reliability

Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach i...

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Main Authors:	Tan, Cher Ming, Raghavan, Nagarajan
Other Authors:	School of Electrical and Electronic Engineering
Format:	Conference or Workshop Item
Language:	English
Published:	2010
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:	https://hdl.handle.net/10356/90793 http://hdl.handle.net/10220/6345
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Institution:	Nanyang Technological University
Language:	English

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spelling	sg-ntu-dr.10356-907932020-03-07T13:24:46Z Statistical modeling of via redundancy effects on interconnect reliability Tan, Cher Ming Raghavan, Nagarajan School of Electrical and Electronic Engineering IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (15th : 2008 : Singapore) Singapore-Massachusetts Institute of Technology (MIT) Alliance DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach is to have an in-built redundancy in the via structures of the interconnect. The presence of redundant via in a parallel topology helps improve the overall reliability of the via structure. Although reliability improvement due to via redundancy is qualitatively understood, it is necessary to quantify the improvement in reliability through statistical models so that the improvement in lifetime as a result of redundancy can be quantified. A statistical model that incorporates the effects of redundancy is developed in this study and it is used to estimate the reliability of redundant via structures. The Cumulative Damage Model (CDM) is used in conjunction with the Maximum Likelihood Estimate (MLE) method to assess the reliability of load sharing via redundant structures in this study. Published version 2010-08-23T06:21:03Z 2019-12-06T17:54:08Z 2010-08-23T06:21:03Z 2019-12-06T17:54:08Z 2008 2008 Conference Paper Raghavan, N., & Tan, C. M. (2008). Statistical modeling of via redundancy effects on interconnect reliability. International Symposium on the Physical and Failure Analysis of Integrated Circuits (pp.1-5) Singapore. https://hdl.handle.net/10356/90793 http://hdl.handle.net/10220/6345 10.1109/IPFA.2008.4588156 en © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 5 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
country	Singapore
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Tan, Cher Ming Raghavan, Nagarajan Statistical modeling of via redundancy effects on interconnect reliability
description	Electromigration is an important failure mechanism in the nano-interconnects of modern IC technology. Various approaches have been investigated to prolong the lifetime of an interconnect. One such approach is to have an in-built redundancy in the via structures of the interconnect. The presence of redundant via in a parallel topology helps improve the overall reliability of the via structure. Although reliability improvement due to via redundancy is qualitatively understood, it is necessary to quantify the improvement in reliability through statistical models so that the improvement in lifetime as a result of redundancy can be quantified. A statistical model that incorporates the effects of redundancy is developed in this study and it is used to estimate the reliability of redundant via structures. The Cumulative Damage Model (CDM) is used in conjunction with the Maximum Likelihood Estimate (MLE) method to assess the reliability of load sharing via redundant structures in this study.
author2	School of Electrical and Electronic Engineering
author_facet	School of Electrical and Electronic Engineering Tan, Cher Ming Raghavan, Nagarajan
format	Conference or Workshop Item
author	Tan, Cher Ming Raghavan, Nagarajan
author_sort	Tan, Cher Ming
title	Statistical modeling of via redundancy effects on interconnect reliability
title_short	Statistical modeling of via redundancy effects on interconnect reliability
title_full	Statistical modeling of via redundancy effects on interconnect reliability
title_fullStr	Statistical modeling of via redundancy effects on interconnect reliability
title_full_unstemmed	Statistical modeling of via redundancy effects on interconnect reliability
title_sort	statistical modeling of via redundancy effects on interconnect reliability
publishDate	2010
url	https://hdl.handle.net/10356/90793 http://hdl.handle.net/10220/6345
_version_	1681045715843809280

Statistical modeling of via redundancy effects on interconnect reliability

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